An analog-to-digital converter (ADC) is supposed to decide at a given recurring point in time whether the input signal is above or below a given threshold. A plurality of thresholds then yields a digital representation of the signal at a certain point in time of the clocking period. In the case of a conventional ADC, the input signal has to be filtered (anti-aliasing filter) prior to the conversion. In this process, noise or non-linearities can interfere with the input signal. An active filter consumes additional energy. In order to avoid a fluctuation of the point in time of the detection, efforts are also aimed at generating edges that are as sharp as possible for the clock signal. Due to parasitic coupling, such edges cause interferences in the internal signals of the ADC, in other words, for example, also in the reference voltages with which the input signal is compared. These fluctuations give rise to erroneous decisions by the comparators.
In this context, International patent document WO 99/13583 discloses a system and a method for correcting a comparator offset that occurs during the operation of an analog-to-digital converter.